IBIS Macromodel Task Group Meeting date: 15 May 2007 Members (asterisk for those attending): * Ambrish Varma, Cadence Design Systems * Arpad Muranyi, Intel Corp. Barry Katz, SiSoft * Bob Ross, Teraspeed Consulting Group * Doug White, Cisco Systems Essaid Bensoudane, ST Microelectronics Ganesh Narayanaswamy, ST Micro Hemant Shah, Cadence Design Systems Ian Dodd, Mentor Graphics Joe Abler, IBM * John Angulo, Mentor Graphics John Shields, Mentor Graphics Ken Willis, Cadence Design Systems * Kumar, Cadence Design Systems Lance Wang, Cadence Design Systems Luis Boluna, Cisco * Michael Mirmak, Intel Corp. Mike LaBonte, Cisco Systems * Mike Steinberger, SiSoft Patrick O'Halloran, Tiburon Design Automation Paul Fernando, NCSU * Radek Biernacki, Agilent (EESof) * Randy Wolff, Micron Technology Ray Comeau, Cadence Design Systems * Richard Ward, Texas Instruments Sanjeev Gupta, Agilent Shangli Wu, Cadence Stephen Scearce, Cisco Systems Syed Huq, Cisco Systems Syed Sadeghi, ST Micro * Todd Westerhoff, SiSoft Vikas Gupta, Xilinx Vuk Borich, Agilent * Walter Katz, SiSoft -------------------------- Call for patent disclosure: No one declared a patent. ----- Opens: ------------- Review of ARs: - Arpad: Review the new macro library files. TBD - Arpad: Write parameter passing syntax proposal for a possible BIRD TBD ------------- New Discussion: Todd Westerhoff discussed the IBIS Summit Presentation to be presented in a couple of weeks in San Diego - Todd has a description, title, and asked for time - LTI versus non-LTI discussion should go into this prez - Status of the BIRD, fundamental concepts should be included - Arpad asked if BIRD would actually be ready by then - Todd said that meetings between EDA vendors are essentially complete - Probably close enough to make an initial BIRD Todd Westerhoff presented the latest version of the BIRD document - Front matter stays pretty much the same as last version - Some changes in the keywords section - Parameter definitions have been firmed up and fleshed out - what's required and what's optional needs refinement - TI, IBM have been regular attendees at the meetings to put this together - Intel, ST Micro recent regulars - EDA companies have been Cadence, SiSoft, Mentor, Agilent - Arpad asked what the model-makers will use to make their models, in terms of languages? - Todd answered any language at all, as long as the result conforms to the API definition - Kumar said that the final "wrapper" must be in C - There could be a cookbook for helping non-programmer types - Parameter discussion: - received parameter thusly: -name - question is, can the "format" change, depending on context? - yes it can - Question came up related to corners: - What if interconnect models only have a "min" format, but TX and RX models only have "max"? - Should we specify what is absolutely necessary? - What exactly do "max" and "min" mean? - Richard Ward from TI said that they have up to 27 different corners that simulate internally, but boil it down to a few corners when releasing models/simulator to customer. - It looks like we need to constrain the allowable list of data formats, depending on the parameter. - It was mentioned that there will probably be receiver models in near future will be able to accept a forwarded clock. There will be more discussion about this in the meetings between the EDA vendors and the chip vendors. Todd and Bob Ross discussed how this document could be made to conform to a formal "IBIS Bird Document". Bob said that most of this proposal could be put into a separate section of the IBIS specification, because so much of it is descriptive content, and therefore it could be plugged in as a complete module and remain untouched, for the most part. The new keywords and subparameters would be embedded into the IBIS structural section. AR: Everone review the proposal, prepare to discuss next week. AR: Mike will upload it to the website. AR: Doc will be sent out to the mailer as well. Next meeting: 22 May 2007 12:00pm PT